The LPC5410x are ARM Cortex-M4 based microcontrollers for embedded applications. These devices include an optional ARM Cortex-M0+ coprocessor， 104 kB of on-chip SRAM， up to 512 kB on-chip flash， five general-purpose timers， one State-Configurable Timer with PWM capabilities （SCTimer/PWM）， one RTC/alarm timer， one 24-bit Multi-Rate Timer （MRT）， a Repetitive Interrupt Timer （RIT）， a Windowed Watchdog Timer （WWDT）， four USARTs， two SPIs， three Fast-mode plus I2C-bus interfaces with high-speed slave mode， and one 12-bit 5.0 Msamples/sec ADC. The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low power consumption， enhanced debug features， and a high level of support block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline， uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals， and includes an internal prefetch unit that supports speculative branching. The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A hardware floating-point unit is integrated in the core. The ARM Cortex-M0+ coprocessor is an energy-efficient and easy-to-use 32-bit core which is code and tool-compatible with the Cortex-M4 core. The Cortex-M0+ coprocessor offers up to 100 MHz performance with a simple instruction set and reduced code size. In LPC5410x， the Cortex-M0 coprocessor hardware multiply is implemented as a 32-cycle iterative multiplier.