The foundation of the ADS1251/52 is the sigma-delta modulator. Although detailed theory of this class of

　　data converter is beyond the scope of this application report， the fundamental operation of this converter is

　　discussed. Figure 2 shows a first-order sigma-delta modulator， which operates as follows.

　　The modulator’s function is to reduce the error between the input signal and the previous output to zero.

　　Assuming a dc input at A， this dc value is applied to a summing point and added to the value from the

　　DAC， E. If the output from the summing junction is positive， the integrator output continues to ramp up

　　until it trips the comparator. The comparator then signals to the DAC that the input has passed its upper

　　threshold. In turn， the DAC then begins to reduce the effective signal at B， and the integrator begins to

　　ramp down. The integrator continues to ramp down until it trips the comparator again. The comparator

　　then signals to the DAC that the input has passed its lower threshold. In turn， the DAC then begins to

　　increase the effective signal at B， and the integrator begins to ramp up again.

　　Because the comparator is latched， this action performs the quantization in time of the analog signal. The

　　quantization in amplitude is accomplished through the density of the pulses originating from the

　　comparator. If the input signal is close to full scale， more 1 pulses occur than 0 pulses in the bit stream

　　from the comparator. Conversely， if the input-signal is close to negative full scale， more 0 pulses occur

　　than 1 pulses in the bit stream from the comparator. Signals near midscale have equal numbers of 1 and

　　0 pulses. Figure 3 shows this graphically.