作者：Anton Patyuchenko，ADI 現(xiàn)場(chǎng)應(yīng)用工程師

Question：

問(wèn)題：

What is the right frequency generation component for my application？

何種頻率產(chǎn)生器件適合我的應(yīng)用？

Answer：

答案：

Understanding the performance characteristics of frequency generation components is critical to determining the right solution for the target use case. This is a quick guide meant to help RF system engineers through the selection process.

了解頻率產(chǎn)生器件的性能特征對(duì)于為目標(biāo)使用場(chǎng)景確定正確的解決方案至關(guān)重要。這是一個(gè)快速指南，旨在幫助RF系統(tǒng)工程師熟悉整個(gè)選擇流程。

Key Performance Criteria

主要性能判據(jù)

Let us first define the criteria that are typically used to characterize the performance of frequency generation components. The most basic one we would normally start our selection process with is the output frequency range. There is a broad variety of components designed to generate frequencies across the entire spectrum， supporting ranges limited to a single tone or spanning multiple octaves. However， when selecting a component based on its output frequencies， it is important to consider that wideband and high frequency capabilities are often traded off for other fundamental characteristics， which include frequency stability， output spectral purity， and switching speed.

我們首先定義表征頻率產(chǎn)生器件性能通常使用的判據(jù)。選擇流程一般從最基本的判據(jù)開(kāi)始，那就是輸出頻率范圍。為了生成整個(gè)頻譜范圍內(nèi)的頻率，人們?cè)O(shè)計(jì)了各種各樣的器件，支持從單音到跨越多個(gè)倍頻程的頻率。然而，當(dāng)根據(jù)輸出頻率選擇器件時(shí)，必須注意到，寬帶和高頻能力常被用來(lái)交換其他基本特性，包括頻率穩(wěn)定性、輸出頻譜純度和開(kāi)關(guān)速度。

Frequency stability represents short-term and long-term variations in the output signal. Short-term stability is associated with variations that are much smaller than one complete period of the signal. These variations are expressed in terms of phase jitter and phase noise. Phase jitter defines small fluctuations in the phase of a signal in the time domain， and the phase noise is its spectral representation described by the relative noise power level contained in a 1 Hz bandwidth at various offsets from the carrier frequency. If the frequency variations occur over a longer period of time， we usually talk about long-term stability， which describes the drift of the output frequency （typically expressed in parts per million or ppm） due to various aspects including temperature， load conditions， and aging.

頻率穩(wěn)定性代表輸出信號(hào)的短期和長(zhǎng)期變化。短期穩(wěn)定性與遠(yuǎn)小于一個(gè)完整信號(hào)周期的變化有關(guān)。這些變化以相位抖動(dòng)和相位噪聲表示。相位抖動(dòng)定義時(shí)域中信號(hào)相位的微小波動(dòng)，相位噪聲是其頻譜表示，由相對(duì)于載波頻率的不同偏移頻率下1 Hz帶寬中包含的相對(duì)噪聲功率水平來(lái)描述。如果頻率變化發(fā)生在較長(zhǎng)時(shí)間段內(nèi)，我們通常會(huì)使用長(zhǎng)期穩(wěn)定性來(lái)描述，它是指由于溫度、負(fù)載條件、老化等各方面導(dǎo)致的輸出頻率漂移（通常用ppm表示）。

Spectral purity is another important characteristic to be considered in the component’s selection process. It is described by the spurious content present in the output spectrum of a device， which is usually quantified by the level of harmonics and feedthrough components expressed relative to the level of the fundamental frequency.

頻譜純度是器件選擇流程中要考慮的另一個(gè)重要特性。它由器件輸出頻譜中存在的雜散成分來(lái)描述，通常用相對(duì)于基頻水平表示的諧波水平和饋通分量來(lái)量化。

In addition to the stability and spectral purity of the output signal， the switching speed （also known as settling time or lock time） is yet another typical trade-off parameter that needs to be considered when choosing the optimum frequency generation solution. It describes how much time it takes for the component to switch from one frequency to another frequency， and this requirement can largely vary depending on the final application.

除了輸出信號(hào)的穩(wěn)定性和頻譜純度之外，開(kāi)關(guān)速度（也稱為建立時(shí)間或鎖定時(shí)間）是又一個(gè)典型的權(quán)衡參數(shù)，選擇最優(yōu)頻率產(chǎn)生器方案時(shí)需要予以考慮。它描述器件從一個(gè)頻率切換到另一個(gè)頻率所需的時(shí)間，此要求可能會(huì)因最終應(yīng)用而有很大差異。

The Main Types of Components

器件的主要類型

Now that we have defined the key performance criteria used to characterize frequency generation components， let us give a short overview of their main types， which are designed to offer different sets of characteristics associated with these criteria. This overview should ultimately serve as a guide to choosing the right type of device， which should meet the needs of the target application.

上面定義了用于表征頻率產(chǎn)生器件的主要性能判據(jù)，現(xiàn)在我們簡(jiǎn)要說(shuō)明其主要類型，這些類型旨在提供與這些判據(jù)相關(guān)的不同特性組合。此概述最終應(yīng)作為選擇正確類型器件以滿足目標(biāo)應(yīng)用需求的指南。

A crystal （XTAL） oscillator （XO） is a component that uses a piezoelectric resonator （typically quartz） to generate fixed output frequency from a few kilohertz up to several hundred megahertz. A special type of XO called a voltage controlled crystal oscillator （VCXO） allows the frequency to be altered， but only by a very small amount to enable fine adjustments. XOs are electromechanical transducers with extremely high Q factors that can exceed 100，000， resulting in a very stable output frequency characterized by a very low phase noise. XOs are limited in their maximum output frequency and tuning capabilities; however， they are the perfect choice when a single precise reference needs to be provided to other types of components to derive much higher frequencies.

晶體（XTAL）振蕩器（XO）使用壓電諧振器（通常為石英）產(chǎn)生幾千赫茲至幾百兆赫茲的固定輸出頻率。有一種特殊類型的XO，稱為壓控晶體振蕩器（VCXO），它允許改變頻率，但只能改變很小的量以支持微調(diào)。XO是具有極高Q因子（可超過(guò) 100，000）的機(jī)電換能器，可產(chǎn)生非常穩(wěn)定且相位噪聲非常低的輸出頻率。XO的最大輸出頻率和調(diào)諧能力有限，但是，當(dāng)需要為其他類型的器件提供單一精確參考以獲得更高頻率時(shí)，它是出色的選擇。

A voltage controlled oscillator （VCO） is a different type of a frequency generation component that relies on LC resonant circuits. Electrical circuit elements result in significantly lower Q factors compared to crystals （typically by a factor of 1000 less）; however， they enable much higher output frequencies and wide tuning ranges. VCOs produce an output signal whose frequency is controlled by an external input voltage. A VCO’s core can use different resonant circuits. Single-core VCOs using high Q resonators offer a low phase noise performance over a limited frequency range， whereas the oscillators designed for a lower Q factor target a wideband operation with mediocre noise characteristics. Multiband VCOs using several switched high Q resonator circuits offer a compromise solution that provides wideband operation and low phase noise performance that is achieved at the expense of a slower tuning speed limited by the time required to switch between different cores. VCOs are a great all-around solution， but they generally do not provide a stable output signal， which is why VCOs are often used in conjunction with phase-locked loops （PLLs） to improve output frequency stability.1

壓控振蕩器（VCO）是一種不同類型的頻率產(chǎn)生器件，依賴于LC諧振電路。與晶體相比，電氣電路元件的Q因子要低得多（通常低1000倍），但它可以實(shí)現(xiàn)高得多的輸出頻率和寬調(diào)諧范圍。VCO產(chǎn)生的輸出信號(hào)頻率由外部輸入電壓控制。VCO的內(nèi)核可以使用不同的諧振電路。使用高Q諧振器的單核VCO可在有限頻率范圍內(nèi)提供低相位噪聲性能，而較低Q因子的振蕩器以寬帶操作為目標(biāo)，噪聲特性很一般。使用多個(gè)切換式高Q諧振器電路的多頻段VCO是一種折衷解決方案，既支持寬帶操作，又能提供低相位噪聲性能，但其代價(jià)是調(diào)諧速度較慢，因?yàn)榍袚Q不同的核需要時(shí)間。VCO是一種出色的全方位解決方案，但它一般不能提供穩(wěn)定的輸出信號(hào)，這就是為什么VCO經(jīng)常與鎖相環(huán)（PLL）配合使用以提高輸出頻率穩(wěn)定性的原因1。

A phase-locked loop （PLL） or PLL synthesizer is a circuit that ensures the stability of a VCO output frequency required in many frequency synthesis and clock recovery applications. As depicted in Figure 1a， a PLL incorporates a phase detector that compares a divide-by-N version of the VCO frequency to the reference frequency and uses this difference output signal to adjust the DC control voltage applied to the tuning line of the VCO. This allows for instantaneous correction of any frequency drift and， thus， maintenance of the stable operation of the oscillator. A typical PLL IC includes an error detector （a phase frequency detector， or PFD， with a charge pump） and a feedback divider （see the dashed line area in Figure 1a）， and it still requires an additional external loop filter， a precise reference frequency， and a VCO to form a complete feedback system for stable frequency generation. The realization of this system can be significantly simplified by using synthesizer ICs featuring an integrated VCO.1，2

鎖相環(huán)（PLL）或PLL頻率合成器可確保許多頻率合成和時(shí)鐘恢復(fù)應(yīng)用所需的VCO輸出頻率穩(wěn)定。如圖1a所示，PLL包含鑒相器，其將VCO頻率的N分頻與參考頻率進(jìn)行比較，并使用該差值輸出信號(hào)調(diào)節(jié)施加于VCO調(diào)諧線路的DC控制電壓。這使得任何頻率漂移都能得到即時(shí)校正，因而振蕩器能夠保持穩(wěn)定工作。典型的PLL IC包含誤差檢測(cè)器（帶電荷泵的鑒頻鑒相器或PFD）和反饋分頻器（參見(jiàn)圖1a中的虛線區(qū)域），另外還需要外部環(huán)路濾波器、精密參考頻率和VCO以構(gòu)成一個(gè)完整的反饋系統(tǒng)，從而產(chǎn)生穩(wěn)定的頻率。使用集成VCO的頻率合成器IC可以大大簡(jiǎn)化該系統(tǒng)的實(shí)現(xiàn)1，2。

Synthesizers with integrated VCO combine a PLL and a VCO in a single package and require only an external reference and a loop filter to realize the desired function. An integrated PLL synthesizer is a versatile solution with a broad spectrum of digital control settings for accurate frequency generation. It may often include integrated power splitters， frequency multipliers， frequency dividers， and tracking filters to permit up to several octaves of frequency coverage beyond the fundamental range of the integrated VCO. The intrinsic parameters of all these components determine the output frequency range， phase noise， jitter， lock time， and other characteristics representing the overall performance of the synthesizer circuit.1

集成VCO的頻率合成器將PLL和VCO組合在單個(gè)封裝中，只需要外部參考和環(huán)路濾波器就能實(shí)現(xiàn)所需的功能。集成式PLL頻率合成器是一種多功能解決方案，具有廣泛的數(shù)字控制設(shè)置，支持產(chǎn)生精確頻率。它常常包含集成功分器、倍頻器、分頻器和跟蹤濾波器，頻率覆蓋范圍超越了VCO的基頻范圍，達(dá)到數(shù)個(gè)倍頻程。所有這些元件的內(nèi)在參數(shù)決定了輸出頻率范圍、相位噪聲、抖動(dòng)、鎖定時(shí)間和其他表示頻率合成電路總體性能的特性1。

A translation loop is another type of synthesizer solution based on the PLL concept but implemented using a different approach. As shown in Figure 1b， it uses an integrated downconversion mixing stage instead of an N-divider in the feedback loop to set the loop gain to 1 and minimize the in-band phase noise. Translation loop ICs （see the dashed line area in Figure 1b） are designed for highly jitter sensitive applications and， in combination with an external PFD and an LO， enable a complete frequency synthesis solution offering instrument-grade performance in a compact form factor.1

轉(zhuǎn)換環(huán)路是基于PLL概念的另一類頻率合成器，但采用不同的方法實(shí)現(xiàn)。如圖1b所示，其反饋環(huán)路中使用的是集成下變頻混頻級(jí)，而不是N分頻器，環(huán)路增益設(shè)置為1，帶內(nèi)相位噪聲極小。轉(zhuǎn)換環(huán)路IC（參見(jiàn)圖1b中的虛線區(qū)域）專為對(duì)抖動(dòng)高度敏感的應(yīng)用而設(shè)計(jì)，并與外部PFD和LO組合使用，以緊湊的尺寸實(shí)現(xiàn)完整的頻率合成解決方案，提供儀表級(jí)性能1。

A direct digital synthesizer （DDS） is an alternative to integrated PLL synthesizers realized using a different concept. The basic DDS architecture is schematically depicted in Figure 1c. It is a digitally controlled system that includes a highly accurate reference frequency representing a clock signal， a numerically controlled oscillator （NCO） creating a digital version of the target waveform， and a digital-to-analog converter （DAC） delivering the final analog output. DDS ICs offer rapid switching speeds， fine tuning resolution of the frequency and phase， and low output distortion， which make them an ideal solution for the applications where superior noise performance and high frequency agility are of primary importance.1，3

直接數(shù)字頻率合成器（DDS）是集成PLL頻率合成器的替代方案，采用不同的原理實(shí)現(xiàn)?；綝DS架構(gòu)的原理圖如圖1c所示。它是一種數(shù)字控制系統(tǒng)，包括表示時(shí)鐘信號(hào)的高精度參考頻率、創(chuàng)建目標(biāo)波形數(shù)字版本的數(shù)字控制振蕩器（NCO）以及提供最終模擬輸出的數(shù)模轉(zhuǎn)換器（DAC）。DDS IC提供非常快的開(kāi)關(guān)速度、精細(xì)的頻率和相位分辨率以及低輸出失真，因此特別適合于出色噪聲性能和高頻率捷變性至關(guān)重要的應(yīng)用1，3。

Conclusion

結(jié)論

Frequency generation components are used in a broad range of applications fulfilling various functions including frequency conversion， waveform synthesis， signal modulation， and clock signal generation. This article presented a brief overview of the main types of these components designed to address different sets of requirements imposed by final applications. For example， communication systems require low in-band noise to maintain low error vector magnitude （EVM）， spectrum analyzers rely on local oscillators with fast lock time to realize rapid frequency sweep， and high speed converters need a low jitter clock to ensure high SNR performance.

頻率產(chǎn)生器件應(yīng)用廣泛，可實(shí)現(xiàn)各種功能，包括變頻、波形合成、信號(hào)調(diào)制和時(shí)鐘信號(hào)產(chǎn)生。針對(duì)最終應(yīng)用施加的不同要求，需要設(shè)計(jì)不同類型的頻率產(chǎn)生器件，本文簡(jiǎn)要說(shuō)明了這些器件的主要類型。例如，通信系統(tǒng)需要低帶內(nèi)噪聲以維持低誤差矢量幅度（EVM），頻譜分析儀依賴于具有快速鎖定時(shí)間的本振來(lái)實(shí)現(xiàn)快速頻率掃描，高速轉(zhuǎn)換器需要低抖動(dòng)時(shí)鐘以確保高SNR性能。

Figure 1. Simplified block diagrams of the （a） PLL， （b） translation loop， and （c） DDS.

圖1.（a） PLL、（b） 轉(zhuǎn)換環(huán)路、（c） DDS的簡(jiǎn)化框圖

Analog Devices provides the broadest portfolio of RF integrated circuits in the industry fitting nearly all of the functional blocks in a signal chain. ADI products deliver best-in-class performance and address the most demanding requirements across a wide variety of RF applications ranging from communication and industrial systems， all the way up to test and measurement equipment and aerospace systems.

ADI公司提供非常豐富的RF集成電路產(chǎn)品組合，支持信號(hào)鏈中的幾乎所有功能模塊。ADI產(chǎn)品提供一流的性能，可滿足廣泛RF應(yīng)用——從通信和工業(yè)系統(tǒng)一直到測(cè)試測(cè)量設(shè)備和航空航天系統(tǒng)——的最苛刻要求。

References

參考資料

1 Anton Patyuchenko. “RF Signal Chain Discourse—Part 2： Essential Building Blocks.” Analog Dialogue， Vol. 55， No. 3， July 2021.

Anton Patyuchenko?！敖饷躌F信號(hào)鏈—第2部分：基本構(gòu)建模塊”?！赌M對(duì)話》，第55卷第3期，2021年7月。

2 Ian Collins and David Mailloux. “Revolution and Evolution in Frequency Synthesis： How PLL/VCO Technology Has Increased Performance， Decreased Size， and Simplified Design Cycle.” Analog Devices， Inc.， January 2020.

Ian Collins和David Mailloux?！邦l率合成技術(shù)的變革和發(fā)展：PLL/VCO技術(shù)如何提升性能、減小尺寸并簡(jiǎn)化設(shè)計(jì)周期”。ADI公司，2020年1月。

3 Jim Surber and Leo McHugh. “Single-Chip Direct Digital Synthesis vs. the Analog PLL.” Analog Dialogue， Vol. 30， No. 3， July 1996.

Jim Surber和Leo McHugh。“單芯片直接數(shù)字頻率合成與模擬PLL”。《模擬對(duì)話》，第30卷第3期，1996年7月。

About the Author

作者簡(jiǎn)介

Anton Patyuchenko received his Master of Science in microwave engineering from the Technical University of Munich in 2007. Following his graduation， Anton worked as a scientist at German Aerospace Center （DLR）。 He joined Analog Devices as a field applications engineer in 2015 and is currently providing field applications support to strategic and key customers of Analog Devices specializing in RF applications. He can be reached at anton.patyuchenko@analog.com.

Anton Patyuchenko于2007年獲得慕尼黑技術(shù)大學(xué)微波工程碩士學(xué)位。畢業(yè)之后，Anton曾在德國(guó)航空航天中心（DLR）擔(dān)任科學(xué)家。他于2015年加入ADI公司擔(dān)任現(xiàn)場(chǎng)應(yīng)用工程師，目前為ADI公司戰(zhàn)略與重點(diǎn)客戶提供現(xiàn)場(chǎng)應(yīng)用支持，主要負(fù)責(zé)RF應(yīng)用。