At breaker-points opening, the shaping circuit (not shown in drawing) produces a square impulse having 2 mS. This, named BP, is applied to EID by an OR gate and generate the main spark.

In multi-spark module, during 2 mS interval, a sequence timer (a counter with decoded outputs) accomplishes the initialization of circuits (full operations will be detailed later). When impulse BP disappears, the gate P2 is opened and the counter N1 receives impulses with 1 mS period, from clock generator. This 8 bits counter measures, in fact, the duration between two breaker-points impulses. It can count maximum 255 impulses, each having 1 mS (see the table, this correspond to 120 rpm, far below the free running speed !). At next BP impulse, P2 close and the counting stop. The number stored inside N1 is in fact the time length between two BP impulses.

The sequence timer “copy” the number stored in N1 to N2, after this resets counter N1. When BP becomes low level, N1 restarts the counting. In the same time, the up/down counter N2, starts counting the impulses having 0.5 mS period, which comes via gate P1. It counts down, but with double speed. In this way the counter N2 reach to “0” after T/2 time. The counter N4 and gate P5 makes the impulses for supplementary sparks (2 mS length).

This counter works only if INH signal is at low level. The fip-flop FF1 “marks” the interval T/2 in which will be generated supplementary sparks. It is reseted when N2 reach “0”. The gates P3 and P4 unlock the flio-flop and start supplementary sparks. Also, these gates switch-off the multi-spark function when engine speed limit is reached (in this case, ~ 2000 rpm). How works this ? In the upper table we can see at about 2000 rpm, the time length between two BP impulses is 15 mS.

This means as after a counting cycle, the first 4 bits of counter N1 will be 111 and next 4, 0000. In this case, P3 gate output will be at low level, and the same value for P4 output. The flip-flop FF1 will be not set, and as result, no supplementary sparks. If the speed engine decrease (time length T increase), the last 4 bits of N1 will have at least one 1 and the flip-flop will be set. This allow to appear supplementary sparks until flip-flop will be reseted by borrow impulse of N2.
The module can be maked like a plug-in adapter for an EID.